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AR# 35055

Virtex-6 FPGA GTX Transceiver - Automatic Macro Insertion for Unused GTX Transceivers


Starting in ISE Design Suite 12.1, MAP automatically inserts a Delay Aligner protecting macro on all GTX Transceivers in a Virtex-6 FPGA.


Macro Description

Starting in ISE Design Suite 12.1, MAP inserts a macro that instantiates each transceiver that is not already being used by the design. This macro protects from the Delay Aligner performance degradation causing RXRECCLK Static Operating Behavior. The macro only instantiates unused GTX Transceivers and does not use any additional logic or routing.

Known Issues

  • Additional power usage: Those GTX Transceivers instantiated by the macro use additional power to what would otherwise be consumed by an unused transceiver. These numbers are included in the PA power estimation tool in 12.1, and will be added to the XPE power estimation spreadsheets.




    30.5 mA

    41.9 mA


    25.7 mA

    26.9 mA

  • Netgen Discrepancies: Netgen removes the inserted macro from the design for post-MAP/PAR timing simulations. This does not impact the results of the simulation and allows simulations to run faster. (Xilinx Answer 35514) discusses this issue in greater depth.

Disabling Macro Insertion

If the Delay Aligner is not used (*), it is possible to disable the MAP feature which inserts the macro. There are two different methods available, depending on the version of tool being used. In 12.1, the user can create the following environment variable which disables any macro insertion:


This work-around is only valid for ISE Design Suite 12.1. In 12.2, more granular disabling is possible via the PROHIBIT UCF constraint. Using the prohibit constraint on a specific GTX location keeps MAP from inserting the macro on that specific GTX.

For example:
See (Xilinx Answer 38933).

Note that 12.2 only supports the PROHIBIT constraint for disabling macro insertion. TheXIL_MAP_NO_INSERT_GTXE1_PWRUP environment variable is not supported for 12.2.

(*) Note

As per Errata EN142, the Delay Aligner is no longer supported. For this reason the DA protecting macro is no longer required.

AR# 35055
Date 02/06/2013
Status Active
Type General Article
  • Virtex-6 SXT
  • Virtex-6 LXT
  • Virtex-6 CXT
  • Virtex-6 HXT
  • ISE Design Suite - 12.1
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