AR# 35061


11.5 EDK, plbv46_slave - Potential BRAM collisions require EDK 12.1 for Spartan-6 production use


The plbv46_slave_burst_v1_01_a, plbv46_slave_single_v1_01_a, plbv46_slave_v1_04_a, rdpfifo_v4_01_a, wrpfifo_v5_00_a and earlier versions have the potential for internal block RAM collisions documented in the "Spartan-6 FPGA Block RAM Resources User's Guide".


Collisions are only possible when the packet FIFO service is included. Other cores which depend on these cores but do not use the packet FIFO service are not affected.  No Xilinx EDK IP cores currently use the packet FIFO service and so are unaffected by this issue. 

This issue might not be reported in simulation and could cause the core to fail in hardware. In summary, core using the read or write packet FIFO service should not be used for production in Spartan-6 until EDK 12.1.

For more information, see (Xilinx Answer 34533).

This issue is scheduled to be fixed to be fixed in EDK 12.2. A 11.5 patch will not be available before 12.1 due to ISE dependencies.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34533 Design Advisory for Spartan-6 FPGA Block RAM - Address Space Overlap N/A N/A
AR# 35061
Date 05/23/2014
Status Archive
Type General Article
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