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AR# 35065

LogiCORE IP Tri-Mode Ethernet MAC v4.4 and earlier - Spartan-6 FPGA block RAM parameterization might result in memory collisions during simulation and erroneous operation

Description

When you target a Spartan-6 FPGA in theLogiCORE Tri-Mode Ethernet MAC version 4.4 and earlier, block RAM collisions can occur in the Example Design Local Link FIFO.

Under certain conditions in which addresses overlap, it is possible that the contents of the Spartan-6 FPGA block RAM can become corrupted. Additional details can be found in the Spartan-6 FPGA Block RAM User Guide (UG383):
http://www.xilinx.com/support/documentation/user_guides/ug383.pdf

Solution

Files named "rx_client_fifo.v[hd]" and "tx_client_fifo.v[hd]" exist in the example_design/fifo subdirectory. In each, there are instances of the primitive RAMB16_S9_S9 which contains attributes called WRITE_MODE_A and WRITE_MODE_B. To work around the issue, change both the WRITE_MODE_A and WRITE_MODE_B values from "READ_FIRST" to "WRITE_FIRST".

This issuewas fixed in version 4.3 rev2, available the ISE design tools 11.5 release of the core, but still exists in the version 4.4 core released in 12.1. This issue isscheduled to be fixed in the next release of the core.
AR# 35065
Date Created 04/05/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LXT
  • Spartan-6 LX
Tools
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • Less
IP
  • Tri-Mode Ethernet MAC