When simulating or running an implemented design in hardware, the MIG Virtex-6 DDR2/DDR3 design might fail calibration for various reasons such as improper board layout or an incorrect pin-out. The calibration algorithm has two stages of read-leveling calibration. However, if a failure is seen, calibration always errors during stage 2 read leveling. Stage 1 does not trigger an error. A failure in read leveling stage 2 is denoted by dbg_rdlvl_done[1:0] = 01.Issues might have occurred during stage 1, but the design does not produce an error flag.
NOTE: This Answer Record is contained in a series of MIG hardware debug Answer Records and assumes you are running the MIG Example Design with the Debug Port Enables. It is best to start at the beginning of this recommended hardware debug flow; see (Xilinx Answer 34588).
NOTE: This Answer Record is a part of the Xilinx MIG Solution Center, see(Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.