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AR# 35091

MIG Virtex-6 and 7 Series DDR2/DDR3 User Interface - app_rdy signal

Description

This part of the MIG Design Assistant will guide you to information on using the app_rdy signal

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

The app_rdy output from the User Interface indicates whether the request currently being submitted to the UI is accepted. If this signal is not asserted by the UI while app_en is asserted, the current request must be submitted again. The app_rdy output will not be asserted if:

  • PHY/Memory initialization is not yet completed.
  • All the bank machines are occupied (can be viewed as the command buffer being full).
  • A periodic read is being inserted.

For information on bank machines and how many commands can be stored at a time, see (Xilinx Answer 35410).

Linked Answer Records

Master Answer Records

Child Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34789 MIG Virtex-6 and 7 Series DDR2/DDR3 User Interface - Signal and Parameter Descriptions N/A N/A
AR# 35091
Date Created 05/24/2010
Last Updated 02/18/2013
Status Active
Type Solution Center
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-7
  • Kintex-7
  • Artix-7
  • Zynq-7000
  • Less
IP
  • MIG