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Write Calibration aligns an entire DQS group to the correct CK clock cycles. This compensates for PCB trace delays and I/O buffer delays that exceed a CK cycle. To perform calibration, clock cycles of delay are added until the desired data pattern is read back. At this time, the correct number of cycles has been determined and write calibration completes. Write Calibration is performed on a per-byte basis.
Write Calibration is performed simultaneously with Read Leveling Stage 2. During this period, multiple writes and reads using the same data pattern (FF00AA5555AA9966) are performed to align write calibration and read calibration properly.The writes are shifted while on the read side bitslip and alignment occurs for different bytes.