We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 35131

11.4 ISE - Generated .fdo file does not work in ModelSim


When a test bench is added to a VHDL library that is different from the work library, my ModelSim simulation does not load.


To resolve this issue the vsim command line will need to modified. The name of the library which the test bench is added to will need to be added to the beginning of test bench entity name. 

For example: library_name.test_bench_entity_name
AR# 35131
Date 05/23/2014
Status Archive
Type Known Issues
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
Page Bookmarked