Description

This Release Note and Known Issues Answer Record is for the SPI-4.2 Lite (POS-PHY L4) v5.2 Core, released in ISE Design Suite 12.1, and contains the following information:

• New Features
• Bug Fixes
• General Information
• Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/userguides/xtp025.pdf

Solution

New Features

• ISE 12.1 software support
• Virtex-6 -1L FPGA support

Bug Fixes

• (Xilinx Answer 34252) Virtex-6 FPGA block RAM resource utilization in v5.1 datasheet is not accurate
• (Xilinx Answer 34562) MMCM Mult values outside of allowable range in Virtex-6 FPGA
• (Xilinx Answer 32920) SPI-4.2 Lite v5.1 - Virtex-6 design might fail timing in PAR

General Information

• Virtex-6 FPGA CXT devices are supported with the following performance:
  -1 speed grade: up to 400 Mb/s
• Multiple Cores: If you are using multiple SPI-4.2 Cores in a single device, see the Multiple Core Instantiation section under the Special Design Consideration chapter of the SPI-4.2 Lite User Guide. It is important to generate multiple cores with unique component names for each instance regardless of core configuration.
• (Xilinx Answer 20430) What is the power consumption of SPI-4.2 Lite Core?
• (Xilinx Answer 20017) Which I/O Standards are supported for SPI-4.2 Core?

Known Issues

• (Xilinx Answer 35270) - SPI-4.2 & SPI-4.2 Lite - Documentation does not describe behavior when partial credit is written

Constraints and Implementation Issues

• DDR mode is not supported in Banks 0 and 2 (top and bottom) in the Spartan-6 LX16 ES device. This only applies to "ES" devices and is fixed in Production Silicon.
  
  Please see the Silicon Spartan-6 FPGA LX16 CES Errata for further information:
  http://www.xilinx.com/support/documentation/spartan-6.htm#131538
• (Xilinx Answer 22009) When implementing an SPI-4.2 Lite design through NGDBuild, several "INFO" and "WARNING" messages appear
• (Xilinx Answer 21998) When implementing an SPI-4.2 Lite design through MAP, several "WARNING" messages appear
• (Xilinx Answer 21999) When implementing an SPI-4.2 Lite design through BitGen, several "WARNING" messages appear
• (Xilinx Answer 22011) There are missing example constraints in the UCF file
• (Xilinx Answer 19999) "ERROR:BitGen:169 - This design contains one or more evaluation cores for which bitstream generation is not supported"

General Simulation Issues

• (Xilinx Answer 34568) MMCM may not lock causing a failure in simulation using VCS
• (Xilinx Answer 21319) TDat Error: Data mismatch error in timing simulation
• (Xilinx Answer 22001) Design example results in warnings for source segmenting packets
• (Xilinx Answer 21350) Demo testbench results in RDat Protocol violation warnings
• (Xilinx Answer 21322) Timing simulation errors: SETUP, HOLD, RECOVERY violations
• (Xilinx Answer 22026) Simulating SPI-4.2 Lite design results in "Error: /X_ODDR HOLD Low VIOLATION ON D1 WITH RESPECT TO C;"
• (Xilinx Answer 35266) - NCSIM Warnings 12.1:ncelab: *W,SDFINF: Instance XIL_ML_UNUSED_DCM_1/CLKFB not found at scope level <top-level> <sdf name>, line <number>.

Hardware Issues

• (Xilinx Answer 20022) When fixed static alignment is used, it is necessary to determine the best IOBDELAY (ISERDES) value or the best DCM setting (PHASE SHIFT) to ensure that the target system contains the maximum system margin and performs across voltage, temperature, and process (multiple chips) variations.