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Important Note: The SPI-4.2 Lite v5.2 core is discontinued in 12.1, and will not be visible in the main CORE Generator tool catalog. You must check the "All IP Versions" check box in order to view, customize and generate the discontinued Core.
Virtex-6 FPGA CXT devices are supported with the following performance: -1 speed grade: up to 400 Mb/s
Multiple Cores: If you are using multiple SPI-4.2 Cores in a single device, see the Multiple Core Instantiation section under the Special Design Consideration chapter of the SPI-4.2 Lite User Guide. It is important to generate multiple cores with unique component names for each instance regardless of core configuration.
(Xilinx Answer 22026) Simulating SPI-4.2 Lite design results in "Error: /X_ODDR HOLD Low VIOLATION ON D1 WITH RESPECT TO C;"
(Xilinx Answer 35266) - NCSIM Warnings 12.1:ncelab: *W,SDFINF: Instance XIL_ML_UNUSED_DCM_1/CLKFB not found at scope level <top-level> <sdf name>, line <number>.
(Xilinx Answer 20022) When fixed static alignment is used, it is necessary to determine the best IOBDELAY (ISERDES) value or the best DCM setting (PHASE SHIFT) to ensure that the target system contains the maximum system margin and performs across voltage, temperature, and process (multiple chips) variations.
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ISE Design Suite - 12.1
SPI-4 Phase 2 Interface Solutions