This Release Notes and Known Issues Answer Record is for the SPI-3 (POS-PHY L3) Link Layer v7.2 Core (released in ISE Design Suite 12.1) and the v7.2 rev1 Core (released as a patch below), and contains the following information:
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide:
Resolved Issues in v7.2
|(Xilinx Answer 34526)||Spartan-6 FPGA core should not be used in production due to potential block RAM memory collision|
|(Xilinx Answer 34264)||Virtex-6 FPGA block RAM resource utilization in 11.4 data sheet is not accurate|
Known issues in v7.2 that are resolved in v7.2 rev1 (see patch below)
|(Xilinx Answer 38850)||SPI-3 Link Layer v7.2 - Data mismatch between rdat and rx_data in Spartan-6 and Virtex-6|
|(Xilinx Answer 38851)||SPI-3 Link Layer v7.2 - Example design simulation testbench monitoring logic not connected|
|(Xilinx Answer 38852)||SPI-3 Link Layer v7.2 - Demo testbench data dropped during simulation|
|(Xilinx Answer 38873)||SPI-3 Link Layer v7.2 - TSX missing for first addr out of TDAT on Virtex-6 and Spartan-6 Devices|
Known Issues in both v7.2 and v7.2 rev1
|(Xilinx Answer 34527)||SPI-3 Link Layer Core - Some designs might fail timing|
|(Xilinx Answer 35266)||NCSIM Warnings 12.1:ncelab: *W,SDFINF: Instance XIL_ML_UNUSED_DCM_1/CLKFB not found at scope level < top-level > < sdf name >, line < number >.|
Download Rev1 Update
To obtain the Rev1 update for Spartan-6 and Virtex-6 FPGAs with resolved issues described above, apply the following patch to the Xilinx ISE 12.2 or later software installation:
Install the patch by extracting the contents of the ".zip" archive to the root directory of the Xilinx ISE software installation.
Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure predefined in the archive.
After installing the patch, regenerate the SPI-3 v7.2 Core in the CORE Generator tool.
For further information on finding the Xilinx install and using environment variables, see (Xilinx Answer 11630).
Note: You might be required to have system administrator privileges to install the patch if you do not have write permissions to the Xilinx Install directory.