We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 35153

11.4 PlanAhead - Incorrect DRC warning in relation to System Monitor auxilliary analog inputs


If any I/Os with an IOStandard other than LVCMOS25 (i.e., LVCMOS33) are locked to the bank where the System Monitor auxiliary analog I/Os are used, the PlanAhead software generates the following DRC error:

Conflicting Vcc voltages in bank I/O Bank 13. For example, the following two terminals locked to this bank have conflicting Vccs. Signal_X of IOStandard LVCMOS33 Vcc 3.3000 & Signal_Y of IOStandard LVCMOS25 Vcc 2.5000"


This is an erroneous warning as the auxiliary analog inputs do not have an IOSTANDARD. The warning can be safely ignored.

Please note that this warning can only be ignored if in relation to the System Monitor auxiliary analog inputs. If both signals in the warning are digital inputs, the warning cannot be ignored.

For details on how to correctly setup the auxiliary inputs, see (Xilinx Answer 29240).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
24537 Virtex-5 System Monitor - What are the FAQs for the System Monitor? N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
29240 Virtex-5 System Monitor - How do you declare I/O pins as auxiliary analog input pins? N/A N/A
AR# 35153
Date 09/04/2017
Status Active
Type General Article
  • PlanAhead - 11.4
Page Bookmarked