AR# 35163: MIG 7 Series and Virtex-6 DDR2/DDR3 - Per-Bit Deskew
MIG 7 Series and Virtex-6 DDR2/DDR3 - Per-Bit Deskew
The MIG 7 Series and Virtex-6 DDR2/DDR3 designs do not include per-bit deskew. Becauseper-bit deskewis not included, what design considerations are necessary to follow?
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Per-bit deskew algorithms are used to align each bit within a DQS group. Because this is not included, it is extremely important to follow the trace matching requirement for a DQS group:
The maximum electrical delay between any DQ and its associated DQS/DQS# should be 5 ps.
For full PCB Layout Guidelines, please see the DDR2/DDR3 SDRAM Memory Solution > Design Guidelines section of UG406for Virtex-6 and UG586 for 7 Series devices.