AR# 35165

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12.1 EDK - Why Does Base System builder allow me to create a design that has timing errors?

Description

Why Does Base System builder allow me to create a design that has timing errors?

Solution

Base System Builder does not guarantee timing if there are 9 slaves or more on the PLB bus.  This problem has been noted for Virtex-6 FPGA designs running at 150 MHz.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34609 12.x EDK - Master Answer Record List N/A N/A
AR# 35165
Date 05/23/2014
Status Archive
Type General Article
Tools
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