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AR# 35168

MIG Virtex-6 DDR2/DDR3 - Stand alone PHY support

Description

The Virtex-6 MIG DDR2/DDR3 design is supported as it is output from the CORE Generator tool with no modifications. Xilinx does not support using the PHY stand alone only. The main reason for this support is the memory controller design includes some "PHY-like" responsibilities that are pertinent for proper operation. Additionally, Xilinx does not provide the timing requirements for the memory controller to PHY interface.

NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

The "PHY-Like" responsibilities performed by the DDR2/DDR3 Memory Controller are sending the periodic reads required for the phase detector circuit and sending ZQ Calibration commands in order to satisfy the JEDEC DDR3 Standard.

Common Questions on PHY Interface Signals:

  • io_config is sent from the controller to configure the direction of the bus (read versus write).
  • io_config_strobe is sent from the controller to tell the PHY when a new value is available on io_config. It is a single pulse.
  • The '0' version of the commands (i.e., ras_n0) are used for row commands (activates) and the "1" version is used for column commands (reads/writes). Thus, the dfi_wrdata_en and dfi_wrdata are only associated with the "1" commands.
  • slot_*_present is only used in multi-rank designs.
Additional Information:

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34718 MIG Virtex-6 DDR2/DDR3 - PHY Architecture N/A N/A
AR# 35168
Date Created 05/21/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG