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AR# 35182

Serial RapidIO v5.5 - VIO example design removed from certain configurations


In the Serial RapidIO v5.5 Core, the ChipScope VIO and ILA cores have been removed from the example design by default to allow the example design to more easily meet timing. Specifically, they have been removed from the Virtex-6, 5.0Gbps, x4 and Spartan-6, 3.125Gbps, x4 device configurations.


The ChipScope cores can be removed or added to the design based on the value of the VIO_SRIO parameter (Verilog) or generic (VHDL) set in the "< component_name >_top.v(hd)" file. When set to '0', the ChipScope cores are not included in the design, when set to '1', the ChipScope cores are added to the design.

To add the ChipScope cores back in to the design for these configurations, change the setting from '0' to '1'.

AR# 35182
Date 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Spartan-6 LX
  • Spartan-6 LXT
  • Less
  • ISE Design Suite - 12.1
  • Serial RapidIO
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