This Answer Record details the items that should be analyzed to verify that Read Leveling Stage 1 of the MIG Virtex-6 DDR2/DDR3 calibration process completed as intended.
For general information on the Read Leveling Stage 1 calibration process, see (Xilinx Answer 35118).
NOTE: This Answer Record is contained in a series of MIG hardware debug Answer Records and assumes you are running the MIG Example Design with the Debug Port Enabled.
It is best to start at the beginning of this recommended hardware debug flow.
NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243).
The Xilinx MIG Solution Center is available to address all questions related to MIG.
Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
Signals of Interest:
Calibration State machine variables (useful ChipScope trigger):
Files of Interest:
The Read Leveling logic is contained in the 'rtl/phy/phy_rdlvl.v/.vhd' module.Debug Steps:
What can go wrong?