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Signals of Interest:
Calibration State machine variables (useful ChipScope trigger):
cal1_state_r = Stage 1 state machine
Byte Count (useful ChipScope trigger):
cal1_cnt_cpt_r = Stage 1 byte being calibrated
Check tap counts:
idel_tap_cnt_cpt_r = Current tap setting for the capture clock
found_edge_r = Asserts when the edge of the window is found
Look at the size of the window found for each byte:
dbg_cpt_first_edge_cnt = First edge of valid window found
dbg_cpt_second_edge_cnt = Second Edge of valid window found
Window size = Second Edge First Edge
Read leveling Complete:
2'b00: Stage 1 and Stage 2 did not finish. 2'b01: Stage 1 of read leveling is complete, stage 2 has not finished. 2'b11: Read Leveling is done.
Files of Interest:
The Read Leveling logic is contained in the 'rtl/phy/phy_rdlvl.v/.vhd' module.
Run the Example Design with Debug Port in hardware and use the above noted Triggers in ChipScope (cal1_state_r and cal1_cnt_cpt_r). Read Leveling Stage 1 is performed for each DQS byte group. The cal1_cnt_cpt_r signal signifies the byte group being calibrated. The debug steps can be performed for each byte group. A failure in any group causes calibration/data errors. It is important to go through the debug steps for each group and note any differences (for example, window size) between the byte groups. This can help narrow down to a specific byte group causing the problems.
Verify the correct Data Pattern is being read back during Read Leveling Stage 1. The debug port includes dbg_rddata which is the captured read data. During read leveling, a single write of the Read Leveling Stage 1 data pattern (FF00FF00FF00FF00) is sent. This data pattern is then continuously read back. Verify this pattern on the dbg_rddata debug signal. If the pattern is not correct, look for stuck bits or a pattern to the incorrect data.
Verify that the IDELAY taps are incrementing. The idel_tap_cnt_cpt_r signal shows the tap count for the capture clock. This value should be incremented during Read Leveling Stage 1.
Calculate the number of edges detected. Depending on the frequency, 0, 1, or 2 edges should be detected. The slower the interface is running, the less edges found. A found edge is detected by the assertion of found_edge_r.
Calculate the window size. This is the difference in taps between the first edge detection and the second edge detection. Look at the values on dbg_cpt_first_edge_cnt and dbg_cpt_second_edge_cnt. The window size in IDELAY taps then equals = dbg_cpt_second_edge_cnt - dbg_cpt_first_edge_cnt. To calculate the window size in ps, multiply the found window taps by the IDELAY tap resolution. This is 52 ps for a REFCLK=300 MHz and 78 ps for a REFCLK=200 MHz.
What can go wrong?
Stuck at bits (or unconnected bits on PCB)
Read and write leveling performed on byte basis, not per-bit
Signal Integrity Issue that affect certain byte lanes
Marginal signal integrity can result in a distorted capture window
Ensure SI Simulations using IBIS are performed
Low frequency results in non-optimal capture settings. Continue to Read Leveling Stage 2 debug when running at low frequencies and no edges were detected.
When swapping bits some bits do not belong to the correct byte
Moving bytes to another column without adjusting certain parameters in the RTL.
Problems with the initial write of calibration data.