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AR# 35196

14.x Timing Analysis - Why are the same source and destination analyzed multiple times in the timing report?

Description

Why are the paths with the same source and destination analyzed multiple times in the timing report?

Examples of this analysis appearin bold:

--------------------------------------------------------------------------------

Timing constraint: TS_CPRI3_CLK = PERIOD TIMEGRP
"I0/U_1/U_0/g0.3.cpri_gtx_inst/GTX_TXOUTCLK_OUT" 3.25 ns HIGH 50%
INPUT_JITTER 0.1 ns;

4881 paths analyzed, 2503 endpoints analyzed, 1 failing endpoint
1 timing error detected. (1 setup error, 0 hold errors, 0 component switching limit errors)
Minimum period is 3.281ns.
--------------------------------------------------------------------------------
Slack (setup path): -0.031ns (requirement - (data path - clock path skew + uncertainty))
Source: I0/U_1/U_1/Ir_core_inst3/U_2/U_5/fifo_we_1d (FF)
Destination: I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/full_inn (FF)

Requirement: 3.250ns
Data Path Delay: 3.166ns (Levels of Logic = 5)
Clock Path Skew: -0.054ns (0.896 - 0.950)
Source Clock: I0/U_1/GTX_TXOUTCLK(3) rising at 0.000ns
Destination Clock: I0/U_1/GTX_TXOUTCLK(3) rising at 3.250ns
Clock Uncertainty: 0.061ns

......

Maximum Data Path at Slow Process Corner: I0/U_1/U_1/Ir_core_inst3/U_2/U_5/fifo_we_1d to I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/full_inn
......

--------------------------------------------------------------------------------
Slack (setup path): -0.006ns (requirement - (data path - clock path skew + uncertainty))
Source: I0/U_1/U_1/Ir_core_inst3/U_2/U_5/fifo_we_1d (FF)
Destination: I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/full_inn (FF)

Requirement: 3.250ns
Data Path Delay: 3.141ns (Levels of Logic = 4)
Clock Path Skew: -0.054ns (0.896 - 0.950)
Source Clock: I0/U_1/GTX_TXOUTCLK(3) rising at 0.000ns
Destination Clock: I0/U_1/GTX_TXOUTCLK(3) rising at 3.250ns
Clock Uncertainty: 0.061ns

......

Maximum Data Path at Slow Process Corner: I0/U_1/U_1/Ir_core_inst3/U_2/U_5/fifo_we_1d to I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/full_inn
......

--------------------------------------------------------------------------------

Solution

Although these paths have the same source anddestination, they are different paths because they have different forks or unique intermediate points. For example, look at the following image and review thetwo paths between FF1 and FF2 below.

So, if you compare the detailed information of the given paths, you will find that they are different.

Examples appear in bold:

Maximum Data Path at Slow Process Corner: I0/U_1/U_1/Ir_core_inst3/U_2/U_5/fifo_we_1d to I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/full_inn
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X155Y12.DQ Tcko 0.283 I0/U_1/U_1/Ir_core_inst3/U_2/U_5/fifo_we_1d
I0/U_1/U_1/Ir_core_inst3/U_2/U_5/fifo_we_1d
SLICE_X149Y9.A4 net (fanout=1) 0.499 I0/U_1/U_1/Ir_core_inst3/U_2/U_5/fifo_we_1d
SLICE_X149Y9.A Tilo 0.061 I1/I0/gxb_interface_inst/gxb_merge_if_inst0/fifo_data_wr_zero(30)
I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/ram_we
SLICE_X153Y3.AX net (fanout=9) 0.457 I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/ram_we
SLICE_X153Y3.COUT Taxcy 0.261 I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/waddr_bin(3)
I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/waddr_bin_next_cry_3
SLICE_X153Y4.CIN net (fanout=1) 0.000 I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/waddr_bin_next_cry_3/O
SLICE_X153Y4.BMUX Tcinb 0.242 I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/waddr_bin(5)
I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/waddr_bin_next_s_5
SLICE_X148Y2.C4 net (fanout=2) 0.559 I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/waddr_bin_next(5)
SLICE_X148Y2.C Tilo 0.061 I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/waddr_gray(4)
I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/waddr_gray_next_0_lut6_2[4]/LUT6
SLICE_X148Y2.B4 net (fanout=1) 0.369 I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/waddr_gray_next(4)
SLICE_X148Y2.B Tilo 0.061 I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/waddr_gray(4)
I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/un7_full_1p_NE
SLICE_X148Y2.AX net (fanout=1) 0.313 I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/un7_full_1p_NE/O
SLICE_X148Y2.CLK Tdick 0.000 I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/waddr_gray(4)
I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/full_inn
------------------------------------------------- ---------------------------
Total 3.166ns (0.969ns logic, 2.197ns route)
(30.6% logic, 69.4% route)
Maximum Data Path at Slow Process Corner: I0/U_1/U_1/Ir_core_inst3/U_2/U_5/fifo_we_1d to I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/full_inn
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X155Y12.DQ Tcko 0.283 I0/U_1/U_1/Ir_core_inst3/U_2/U_5/fifo_we_1d
I0/U_1/U_1/Ir_core_inst3/U_2/U_5/fifo_we_1d
SLICE_X149Y9.A4 net (fanout=1) 0.499 I0/U_1/U_1/Ir_core_inst3/U_2/U_5/fifo_we_1d
SLICE_X149Y9.A Tilo 0.061 I1/I0/gxb_interface_inst/gxb_merge_if_inst0/fifo_data_wr_zero(30)
I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/ram_we
SLICE_X153Y3.AX net (fanout=9) 0.457 I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/ram_we
SLICE_X153Y3.DMUX Taxd 0.448 I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/waddr_bin(3)
I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/waddr_bin_next_cry_3
SLICE_X148Y2.C3 net (fanout=2) 0.527 I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/waddr_bin_next(3)
SLICE_X148Y2.CMUX Tilo 0.173 I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/waddr_gray(4)
I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/waddr_gray_next_0_lut6_2[4]/LUT5
SLICE_X148Y2.B3 net (fanout=2) 0.319 I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/waddr_gray_next(3)
SLICE_X148Y2.B Tilo 0.061 I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/waddr_gray(4)
I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/un7_full_1p_NE
SLICE_X148Y2.AX net (fanout=1) 0.313 I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/un7_full_1p_NE/O
SLICE_X148Y2.CLK Tdick 0.000 I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/waddr_gray(4)
I0/U_1/U_1/Ir_core_inst3/U_2/U_5/tx2rx_inst/full_inn
------------------------------------------------- ---------------------------
Total 3.141ns (1.026ns logic, 2.115ns route)
(32.7% logic, 67.3% route)

AR# 35196
Date Created 10/24/2011
Last Updated 12/15/2012
Status Active
Type General Article
Tools
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