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AR# 35241

LogiCORE IP XAUI v9.2 - Timeout seen in some Virtex-5 FPGA Example Design Timing Simulations


When running timing simulation with the XAUI Virtex-5 FPGA example design, timeouts are sometimes seen.


This can been seen due to timing failures on the XGMII interface which is not constrained.  This interface will typically be connected to internal logic when used in a customer's system.   

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
35239 LogiCORE IP XAUI v9.2 - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A
AR# 35241
Date 05/23/2014
Status Archive
Type General Article
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • ISE Design Suite - 12.1
  • XAUI
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