AR# 35242


MIG Virtex-6 DDR2/DDR3 - Clock Requirements and Modifying the Input Clock Frequency


The Virtex-6 DDR2/DDR3 MIG design has two clock inputs, the reference clock and the system clock input. 

The reference clock drives the IODELAYCTRL components in the design, while the system clock input is used to create all MIG design clocks (used in the user interface, controller, and PHY layers).

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243)

The Xilinx MIG Solution Center is available to address all questions related to MIG. 

Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


Reference Clock (clk_ref)

The IDELAYCTRL reference clock is routed directly to the IODELAY_CTRL primitive instantiated in the top level module. 

The clk_ref input should be driven by either a 200 MHz or 300 MHz input clock. 

The reference clock speed affects the tap size and impacts the effective window over which a signal can be shifted with the IODELAY.

It is important to be able to shift a signal over an entire clock period. 

For more details, and when the MIG design uses a 200 MHz reference clock versus a 300 MHz reference clock, see the (Xilinx Answer 35252)

Clock (sys_clk)

MIG assumes that the input system clock is the same as the interface frequency. 

That is, if you specify a 400 MHz memory interface, the design is setup for a 400 MHz input clock. 

The 400 MHz system clock is fed into an MMCM (located in the infrastructure.v/.vhd module) to create the required MIG clocks:

  • 0.5x (1/2 rate) BUFG clock used to drive User Interface, Controller, and PHY CLB logic
  • 1x BUFG clock used to drive I/O Logic for the DRAM Clocks, Controller, Address, DM, and DQ/DQS
  • 1x Performance Path Clock (CLKPERF) used to create the capture and resynchronization clocks in the read path

For a picture of the clocking scheme, see the PHY Clocking Architecture figure located in the DDR2/DDR3 SDRAM Memory Interface Solutions > Core Architecture > PHY section of theVirtex-6 FPGA Memory Interface Solutions User Guide(UG406):

The Virtex-6 DDR2/DDR3 MIG design is a half rate controller, meaning the controller runs at half the rate of memory interface. 

This makes it easier to meet timing internally for high speed memory interfaces, and makes the data bus 4 times the DQ width to account for rising and falling data.

Using a different input clock rate

MIG assumes the main system clock input is the same rate as the DRAM interface.

If you want to use a different input clock rate, you must make changes to the source code to modify the MMCM settings in the MIG design. 

The MMCM multiply and divide parameters are set in the top level wrapper file (example_top.v/vhd for the example design folder or design_name.v/vhd for the user design folder):

parameter CLKFBOUT_MULT_F = 8,
parameter DIVCLK_DIVIDE = 4,
parameter CLKOUT_DIVIDE = 2,

These are set to create the above MMCM output clocks based on the MMCM input clock.


MIG assigns the memory clock frequency to the top-level tCK parameter.

This tCK parameter is used to create the input clock (CLKIN1_PERIOD) frequency of the MMCM.

It is also used to create counters within the controller design (for example, the refresh counter). 

Because this parameter is used to create the counters, it cannot be modified to the new input clock period. 

A new parameter must be created to assign the input clock period to. 

Once the new parameter is created, it should be used to drive the input clock (CLKIN1_PERIOD) of the MMCM. 

The MMCM is instantiated in the MIG provided infrastructure.v/.vhd module. 

The top-level of both the user_design and the example_design instantiate the infrastructure. 

The Virtex-6 Clocking Wizard can be used to determine the appropriate MMCM M and D values based on the input frequency and required MIG MMCM output clocks (see above).

NOTE: When modifying these parameters, the user must keep in mind of the various restrictions on these MMCM parameters, such as the restriction that CLKFBOUT_MULT cannot be set to 2, 3, or 4. 

To minimize jitter, MIG requires keeping the VCO Frequency at or above 1 GHz.

Calculating Proper VCO Frequency


Additional information

(Xilinx Answer 35113) - Usage of DQS
(Xilinx Answer 35112) - Internally generated capture clock
(Xilinx Answer 43559) - MIG Virtex-6 DDR2/DDR3 - Generating reference clk from existing MMCM resource

Revision History
02/10/2011 - Modified M value in minimizing jitter note from 8 to 10
08/10/2011 - Added Answer Record 43559
06/26/2012 - removed CLKFBOUT_MULT_F must not exceed 10 requirement
09/06/2012 - Minor update

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43559 MIG Virtex-6 DDR2/DDR3 - Generating a Reference clk from an Existing MMCM Resource N/A N/A
35260 MIG Virtex-6 DDR2/DDR3 - Clocking and Reset N/A N/A
AR# 35242
Date 08/29/2014
Status Active
Type Solution Center
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