UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 35251

12.1 EDK, XPS_IIC - Does the XPS_IIC core support clock stretching?

Description

Does the xps_iic support clock stretching as described in the Phillips data sheet?

Solution

Xilinxuses a different term inXPS_IICdata sheet:

Throttle Description

The Philips I2C-bus Specification permits devices to throttle (suspend)
data transmission on the bus by holding the SCL line low for an indefinite
period of time.
(DS606 December 2, 2009, page 24)


From the Philips spec:

3.9 Clock stretching

Clock stretching pauses a transaction by holding the SCL line LOW. The
transaction cannot continue until the line is released HIGH again.
(UM10204, I2C-bus specification and user manual, Rev. 03, 19 June 2007,
http://www.nxp.com/acrobat/usermanuals/UM10204_3.pdf)

AR# 35251
Date Created 07/13/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-3
  • Spartan-3 XA
  • Spartan-3A
  • More
  • Spartan-3A DSP
  • Spartan-3AN
  • Spartan-3E
  • Spartan-6 LX
  • Spartan-6 LXT
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 QPro/R
  • Virtex-4 SX
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
Tools
  • EDK - 10.1
  • EDK - 10.1 sp1
  • EDK - 10.1 sp3
  • More
  • EDK - 11.1
  • EDK - 11.2
  • EDK - 11.3
  • EDK - 11.4
  • EDK - 11.5
  • EDK - 12.1
  • Less
IP
  • XPS IIC Bus Interface