This parameter needs to be modified, as follows, to 300 for DDR3 designs running between 480-533 MHz.
For designs with existing boards, an MMCM needs to be added to the design to multiply the 200 MHz clock up to 300 MHz to then drive the MIG REFCLK clock.
Ensure CLKFBOUT_MULT_F values of 2, 3, and 4 are not used in this MMCM.
See (Xilinx Answer 33849) for more information.
For designs without existing boards, simply choose a 300 MHz clock for the MIG REFCLK input.