We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 35273

11.5 Map -ERROR:Place:1134 - Automatic clock placement failed


I am getting the following error when running through MAP in ISE software 11.5

ERROR:Place:1134 - Automatic clock placement failed. Please attempt to analyze the global clocking required for this
design and either lock the clock placement or area locate the logic driven by the clocks so that the clocks may
be placed in such a way that all logic driven by them may be routed. There are two main restrictions on clock
placement for this architecture. The first is that only 12 of 32 clocks sourced by BUFGs may enter a region. The
second is that all loads of a BUFH must be placed in the same region as the BUFH. For further information, see the
"Clock Resources" section in the V-6 User Guide.
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

In ISE software 12.1, Map passes but leaves a number of unrouted nets in PAR

What is the cause of this error?


This error message can occur for a number of different reasons. In general it means that the placement tools were unable to find a solution for clock configuration in the design. In this particular case the user did not insert a BUFG between the MMCM and its loads and the clock placer did not handle the circuit well. In ISE software 11.5, it failed to find a solution; in ISE software 12.1, it placed the circuit into an unroutable configuration.

The solution is to instantiate a BUFG between the MMCM and the loads. A CR is being investigated to improve the error handling.

AR# 35273
Date 06/01/2010
Status Active
Type Error Message
Page Bookmarked