AR# 35300

11.4 EDK, MicroBlaze - Processor stall occurs when TLB set to inhibit caching

Description

If MicroBlaze v7_02_d is configured with a MMU, writeback caches and c_dcache_always_used=1, and MicroBlaze can stall if the a TLB is configured as inhibit caching. How do I resolve this issue.

Solution

To work around this issue, changing any of above settings should prevent the stalls.

This issue is fixed in MicroBlaze_v7_03_a, to be released in EDK 12.1.

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AR# 35300
Date	04/19/2010
Status	Active
Type	General Article
Devices	Spartan-3 Spartan-3 XA Spartan-3A Spartan-3A DSP Spartan-3AN Spartan-3E Spartan-6 LX Spartan-6 LXT Virtex-4 FX Virtex-4 LX Virtex-4 QPro/R Virtex-4 SX Virtex-5 FXT Virtex-5 LX Virtex-5 LXT Virtex-5 SXT Virtex-5 TXT Virtex-5Q Virtex-6 CXT Virtex-6 HXT Virtex-6 LX Virtex-6 LXT Virtex-6 SXT More Less
Tools	EDK - 11.4 EDK - 11.5
IP	Microblaze

AR# 35300

11.4 EDK, MicroBlaze - Processor stall occurs when TLB set to inhibit caching

Description

Solution

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AR# 35300

11.4 EDK, MicroBlaze - Processor stall occurs when TLB set to inhibit caching

Description

Solution