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AR# 35321

Endpoint Block Plus Wrapper v1.14 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1

Description

This Release Notes and Known Issues Answer Record is for the Endpoint Block Plus Wrapper v1.14, released in ISE Design Suite 12.1, and contains the following information:
  • General Information
  • New Features
  • Bug Fixes
  • Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide (XTP025):
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

New Features
  • ISE 12.1 software support
  • Synplify support added for VHDL
  • Support for Virtex-5Q FPGA
  • License check removed
  • New script added to generate netlist of core.

Resolved Issues

CR 529524: Synplify support now available for top level wrapper
Support for Synplify is now available for both Verilog and VHDL top level wrappers
(As documented in UG341, "Synthesis of the Block Plus core wrapper source code is only supported with XST")

CR 550704: License checks removed
The Virtex-5 FPGA Integrated Block Plus for PCI Express product no longer checks for license and does not require a pre-shipped license as of the ISE 12.1 software release.

CR 555015: Hexadecimal value for Device ID causing simulation failure
Issue resolved where a Hexadecimal value for Device ID caused simulation failure.

CR 551805: VHDL simulation time-out
Issue resolved where VHDL simulation was timing out due to issue in root port test bench.

CR 539288: XST error in 2-lane 250 MHz interface frequency design
Issue resolved where implementing 2-lane designs with 250 MHz interface frequency would result in unrecognized constraint error, due to error in the delivered XCF.

CR 550697: TXBUFDIFFCTRL selection in GUI not displaying correctly
Issue resolved where TXBUFDIFFCTRL display in GUI did not change to match the selected option for TXDIFFCTRL.

CR 536197: PIO Design updated for generating completions for I/O Writes
PIO design updated to enable generation of completion for I/O Writes.

CR 539544: Root Port model provided for Endpoint product now passes Memory / I/O transactions to User side.
Root Port model delivered with the Endpoint product has been updated to pass Memory and I/O transactions from the Endpoint to the User side.

CR 539439: TXBUFDIFFCTRL not driving TXBUFDIFFCTRL on the GT
Issue resolved where the GUI selection of TXBUFDIFFCTRL was not driving the TXBUFDIFFCTRL on the GT.

CR 541047: Incorrect path in delivered XCF for synplify flow
Issue resolved where the delivered XCF for synplify flow had incorrect path for the NETs.

CR 551912: TXPREEMPHASIS selection in GUI fixed
Issue resolved where the GUI was preventing selection of non-default values for TXPREEMPHASIS.

CR 540346: New script to enable generation of ngc for core.
New script delivered, to enable generation of ngc for core

CR 551223: Root Port model settings corrected.
Issue resolved where Root Port model settings were incorrect causing error in simulation, due to incorrect attribute setting on the model.

CR 539017: Warnings during Core Generation from ISE resolved
Issue resolved where Core generation from ISE / Project Navigator caused a number of Warnings to be generated.

Known Issues

There are three main components to the Endpoint Block Plus Wrapper for PCI Express:
  • Virtex-5 FPGA Integrated Block for PCI Express
  • Virtex-5 FPGA GTP/GTX Transceivers
  • Block Plus Wrapper FPGA fabric logic
The known issues for the integrated block and GTP/GTX transceivers are found in the Block Plus Core User Guide (UG341)delivered with the core and found at:
http://www.xilinx.com/support/documentation/ipbusinterfacei-o_pci-express_v5pciexpressblockplus.htm

(Xilinx Answer 31646) - Endpoint Block Plus Wrapper v1.14 for PCI Express - Dual Core UCF problems
(Xilinx Answer 34706) - Endpoint Block Plus Wrapper v1.14 for PCI Express - Disconnecting Packets on TX Interface when Interfacing with a link Partner Advertising Non-Infinite Completion Credits May Eventually Stall the Transmit Interface
(Xilinx Answer 34710) - Endpoint Block Plus Wrapper v1.14 for PCI Express - Extensive deassertion of trn_rnp_ok_n could lock up receive interface
(Xilinx Answer 36783) - Endpoint Block Plus Wrapper v1.14 for PCI Express - Finite completion attribute not set correctly
(Xilinx Answer 37246) - Endpoint Block Plus Wrapper v1.14 for PCI Express - Possible inbound packet loss if a 8b10b error occurs while previous packet is being written into receive block ram

Revision History
9/15/2010 - Added note that CR 529524 only applies to the top level wrapper file, not the Wrapper's source code
8/04/2010 - Added 37246
7/14/2010 - Added 36783
4/23/2010 - Initial Release

Linked Answer Records

Child Answer Records

Associated Answer Records

AR# 35321
Date Created 04/20/2010
Last Updated 05/20/2012
Status Active
Type Release Notes
Devices
  • Virtex-5 FXT
  • Virtex-5 LXT
  • Virtex-5 SXT
Tools
  • ISE Design Suite - 12.1
IP
  • Endpoint Block Plus Wrapper for PCI Express