The issue described in (Xilinx Answer 35681) is fixed in v1.5 and later versions of the wrapper. New Features
ISE 12.1 software support
Added support for HXT devices - 6VHX380T-FF1154, 6VHX380T-FF1923and 6VHX255T-FF1923
Support for 8-lane Gen2 Endpoint product has been enabled for Virtex-6 HXT
Option added to enable Buffering optimized for Bus Mastering Applications
License check removed
CR 550704: License checks removed The Virtex-6 FPGA Integrated Block for PCI Express product no longer checks for license and does not require a pre-shipped license as of the 12.1 release.
CR 522983: Gen2 operation supported with 100 MHz Reference Clock Gen 2 operation is now also supported with 100 MHz Reference Clock.
CR 510476: VHDL example design / testbench for Root Port Configuration now supported VHDL example design and testbench for both the Endpoint and Root Port Configurations is now supported.
CR 531976: Synplify flow now supported in the ISE 12.1 software release Synplify flow is now supported in the ISE 12.1 software release.
CR 535127: Option added to enable Buffering optimized for Bus Mastering application New option has been added to CORE Generator interface to enable Buffering optimized for Bus Mastering applications.
CR 538257: Added support for 6VHX380T-FF1154, 6VHX380T-FF1923 and 6VHX255T-FF1923 Support for all HXT devices has now been enabled.
CR 531975: 8-lane Gen2 product is now supported in the Virtex-6 HXT devices Support for 8-lane Gen2 product, in Virtex-6 HXT devices is now available.
CR 538644: 8-lane Gen2 product is now supported in the Virtex-6 LX130T device, in a -2 speedgrade 8-lane Gen2 product is now supported for 6VLX130T, in a -2 speedgrade, in the 12.1 release.
CR 535128: Root Port product hardware autonomously initiates Gen1-Gen2 speed change The Root Port product now hardware autonomously initiates Gen1 - Gen2 speed change if possible.
CR 548630, 552700, 550490, 545280: GTX Production Settings Updated GTX settings have been updated per Production GTX settings.
CR 551143: Core Generation from ISE software fixed Issue resolved where coregen Generation from ISE was failing.
CR 546697: LL Replay Timer default settings have been changed in GUI LL Replay Timer default settings have been changed in the GUI, as previous values were not accounting for internal processing delays, causing Correctable errors (replays) when there is link traffic but no link errors.
CR 538239: New GUI option added to Disable TX ASPM L0s New GUI options has been added to Disable TX ASPM L0s action. This option is recommended to be enabled for links that interconnect Xilinx Virtex-6 FPGA to any Xilinx component.
CR 539285: Workaround added for De-emphasis Value Error known restriction, for Root Port configuration Work-around has been implemented for the known restriction "De-emphasis Value Error", in the Root Port Configuration, by setting PLDOWNSTREAMDEEMPHSOURCE attribute to 1b. For more information on the restriction, refer to the "Known Restrictions" section in the User Guide.
CR 539545: Root Port model provided for Endpoint product now passes Memory / I/O transactions to User side Root Port model delivered with the Endpoint product has been updated to pass Memory and I/O transactions from the Endpoint to the User side.
CR 552777: Enabled PROM file generation for programming ML605 Enabled PROM file generation for programming ML605, in the implementation scripts.
CR 548864: Upgrade capability added Upgrade capability added to enable generation of the latest version of the product for a previously customized project (from an XCO from the previous version of the core).
CR 553769: Default value of Acceptable L0s Exit Latency changed Default value of the Acceptable L0s Exit Latency for an Endpoint product has been updated to a "Maximum of 64 ns".
CR 531980: GT Debug Ports option removed from CORE Generator GUI GT Debug Ports (DRP) option has been removed from the CORE Generator GUI.
CR 555118: VHDL update The VHDL source code has been updated for latest wrapper changes and also for issues with existing code, which was causing address on Read FIFO to be incorrect.
CR 539219: Constraints added for Configurations with User Clock 250 MHz Constraints were added to the UCF and XCF for Configurations with User Clock set to 250 MHz
CR 537545: PLL reset input changed PLL reset input had been changed so it does not get reset at link-down. This enables the trn_clk to not be interrupted in this scenario.
(Xilinx Answer 33834) - Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - Use of Component Name "core" Causes Implementation Failures using VHDL Flow (Xilinx Answer 34009) - Virtex-6 FPGA ML605 Board - PCI Express Link Will Not Train; Implementations for PCI Express Must Use the v1.3 Integrated Block Wrapper for PCI Express (Xilinx Answer 34115) -Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - WARNING:Xst:2016 - Found a loop when searching source (Xilinx Answer 36019) - Virtex-6 FPGA Integrated Block for PCI Express - Coregen allows generating a x8 Gen 2 design for the XC6VLX550T-2; But this is not supported (Xilinx Answer 36048) - Virtex-6 FPGA Integrated Block for PCI Express - Cannot generate x8 Gen 2 for the XC6VLX365T-3 Part (Xilinx Answer 36677) - Virtex-6 FPGA Integrated Block Wrapper v1.3 rev 2 and v1.5 for PCI Express - Updated MGT Settings (Xilinx Answer 35225) - Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - x8 Gen 2 128-bit VHDL Wrapper Corrupts Received TLP Addresses (Xilinx Answer 37207) - Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - x8 Gen 2 128-bit Wrapper is Not Deasserting trn_tdst_rdy_n When Integrated Block Transmit Buffer is Full (Xilinx Answer 37784) - Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - x8 Gen 2 Timing Closure
Revision History 08/31/2010 - Added 37784 08/09/2010 - Added information about 35681 08/04/2010 - Added 37207 07/14/2010 - Added 35225 and v1.5.1 patch information 07/08/2010 - Added 36677 06/04/2010 - Added 36019, 36048 04/23/2010 - Initial Release