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AR# 35323

Spartan-6 FPGA Integrated Block Wrapper v1.3 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1

Description

This Release Notes and Known Issues Answer Record is for the Spartan-6 FPGA Integrated Block Wrapper v1.3 for PCI Express, released in ISE Design Suite 12.1, and it contains the following information:
  • General Information
  • New Features
  • Bug Fixes
  • Known Issues

For installation instructions, general CORE Generator interface known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

New Features

- ISE 12.1 software support
- VHDL source for testbench
- Support for ISIM
- Additional Part/Package support

Resolved Issues

- V6 MMCM VCO changed from 500 MHz to 1000 MHz (in Root Port Model)
- Version fixed: 1.2 rev 1
- CR #543565
-(Xilinx Answer 34341)

- Timing error when implementing VHDL example design
- Version fixed: 1.2 rev 1
- CR #548007
-(Xilinx Answer 34342)

- Designs which use Multi-Vector MSI should check the number of allocated
vectors before generating an MSI interrupt
- Version fixed: N/A
- Previously mentioned as an issue in v1.1 but no longer an issue in v1.2
- CR #522729
-(Xilinx Answer 32866)



Known Issues

(Xilinx Answer 35115) - Spartan-6 Integrated Block Wrapper v1.3 for PCI Express - Transmitting memory writes eventually introduces corrupt payload
(Xilinx Answer 40626) - Spartan-6 FPGA Integrated Block Wrapper v1.4 and v2.2 for PCI Express - DRC Error During Simulation using Provided Root Port Model

Revision History
03/01/2011 - Added 40626
04/23/2010 - Initial Release

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
40626 Spartan-6 FPGA Integrated Block for PCI Express - DRC Error During Simulation using Provided Root Port Model N/A N/A
AR# 35323
Date Created 04/20/2010
Last Updated 05/20/2012
Status Archive
Type Release Notes
Devices
  • Spartan-6 LXT
Tools
  • ISE Design Suite - 12.1
IP
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )