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AR# 35337

LogiCORE IP Tri-Mode Ethernet MAC - Meeting RGMII setup and hold when targetting Spartan-6 FPGAs


When targeting a Spartan-6 FPGA and using an RGMII interface, theucf offset constraints for the RGMII receive inputsare currently commented out.Tri-Mode Ethernet MAC v4.3 rev1, v4.3 rev2 and v4.4 cores use a DCM to adjust the clock and data relationship, but the RGMII specified 1 ns setup 1 ns hold time is not met in the current speed files.


In ISE 12.2 software and later with the Tri-Mode Ethernet MAC v4.4 rev1, core timing is now met using the DCM to adjust the RGMII receive clock and data relationship.

In ISE 12.2 software and later with the Tri-Mode Ethernet MAC v4.4 rev2, core timing is met using a BUFG on the RGMII RX clock and IDELAYs and the RGMII RX data.

For more information, see (Xilinx Answer 35279) LogiCORE IP Tri-Mode Ethernet MAC v4.4, v4.4rev1 and v4.4rev2 - Release Notes and Known Issues for ISE 12.1 and ISE 12.2 software
AR# 35337
Date Created 04/28/2010
Last Updated 12/15/2012
Status Active
Type General Article