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AR# 35355

LogiCORE IP Initiator, Target v4.12 for PCI - Hold Time Violations When Implementing with the Spartan-6 LX45 or LX45T FPGAs (6slx45 or 6slx45t)

Description


When implementing the 64-bit version of the v41.2core with ISE 12.1 software, you will fail timing with a Hold Time violation. The PAR report will indicate failure on the constraint:
TIMEGRP "CTL_BUS" OFFSET= IN 7 ns VALID7 ns BEFORE COMP "PCLK" TIMEGRP ALL_FFS
And the timing report will indicate:
Timing constraint: TIMEGRP "CTL_BUS" OFFSET = IN 7 ns VALID 7 ns BEFORE COMP "PCLK" TIMEGRP ALL_FFS;
241 paths analyzed, 138 endpoints analyzed, 29 failing endpoints
29 timing errors detected. (0 setup errors, 29 hold errors)
Minimum allowable offset is 4.567ns.

Solution

This is expected to be fixed in ISE 12.2 software. Customers can proto-type and develop with these failures, but should not release product until ISE 12.2 software is available to ensure these paths are correctly timed.

Revision History
04/23/2010 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
35334 LogiCORE IP Initiator, Target v4.12 for PCI - Release Notes and Known Issues for ISE Design Suite 11.4 N/A N/A
AR# 35355
Date Created 07/01/2010
Last Updated 05/19/2012
Status Active
Type Known Issues
Devices
  • Spartan-6 LXT
Tools
  • ISE Design Suite - 12.1
IP
  • 64-bit Initiator/Target for PCI