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AR# 35382

LogiCORE IP Video Scaler v2.0 - Virtex-6 and Spartan-6 core should not be used in production due to potential block RAM memory related problems

Description

The Video Scaler v2.0 Virtex-6 and Spartan-6 FPGA core should not be used in production due to potential block RAM memory related problems.

Solution

These issues are fixed in the Video Scaler v2.1 core, available in 12.1.

The Video Scaler v2.0 has the potential for internal block RAM collisions due to the restriction regarding READ_FIRST mode and asynchronous clocking, documented in the:

(Xilinx Answer 34859) and Virtex-6 FPGA Memory Resources User's Guide(UG363)

(Xilinx Answer 34533) and Spartan-6 FPGA Block RAM Resources User Guide (UG383)

This issue might not be reported in simulation and could cause the core to fail in hardware. As such, the core should not be used for production at this time.

 

The Video Scaler v2.0 in 11.4 and 11.5 has the potential for memory initialization issues as documented in the following Xilinx Answers:

(Xilinx Answer 34659) Spartan-6 FPGA Block RAM - Output Register of BRAM does not Initialize Correctly After Initial Configuration

(Xilinx Answer 34712) Spartan-6 FPGA Block RAM Design Advisory - 9K Simple Dual Port (SDP) Block RAM Initialization Incorrect

 

Please see (Xilinx Answer 31958) for a detailed list of LogiCORE IP Video Scaler Release Notes and Known Issues.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
31958 LogiCORE IP Video Scaler - Release Notes and Known Issues N/A N/A

Associated Answer Records

AR# 35382
Date Created 04/26/2010
Last Updated 05/26/2014
Status Archive
Type General Article
IP
  • Video Scaler