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AR# 35399

12.1 Virtex-6 FPGA Partial Reconfiguration - RAM contents not written correctly to Partial Bitfiles


In ISE 12.1 software, any Virtex-6 FPGA Partial Reconfiguration design which contains RAM within the RPs does not have the RAM contents written correctly to the Partial Bitfiles. This manifests as incorrect functionality when the Partial Bitfiles are loaded into the device, but correct functionality on the initial full configuration.


This issue is scheduled to be fixed in the ISE 12.2 software.

There is a patch available for the ISE 12.1 software that resolves the issue.

Follow the link to file to download the patch.
AR# 35399
Date 05/19/2012
Status Archive
Type Known Issues
  • ISE Design Suite - 12.1
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