This section of the MIG Design Assistant focuses on how command requests by the User/Native Interface are stored.
Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243).
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MIG design for previous architectures included command FIFOs with specific FIFO depths.
This determined the number of commands that could be stored at a time.
The MIG 7 Series and Virtex-6 DDR2/DDR3 design does not include command FIFOs.
Instead, commands are assigned to bank machines.
The number of commands that can be stored is based on the number of bank machines and the traffic generation requested.
Each bank machine holds a single request and the interface will push back until it is processed and the bank machine is freed.
If the user streams a set of requests that are optimal to the reordering algorithm, little or no pushback will occur.
The design also includes a starvation mechanism.
The number of banks machines that can be configured is between 2-8.
By default, MIG uses 4 bank machines.
This is a trade-off between area and performance.
As this number is increased, FPGA logic timing becomes more challenging and timing failures can occur depending on design and memory configuration.
Timing closure should be taken care of by the user.
Based on overall design timing budget and timing score, for 7 series devices, the ExtraNetDelay_high and Explore directives might help to close the timing.
To modify the number of bank machines, open the memc_ui_top module and locate the following parameters:
BM_CNT_WIDTH is the number of bits required to represent the number of bank machines.
nBANK_MACHs is the number of bank machines to be configured in the design.
For 7 Series devices the ability to specify the number of bank machines was added to the MIG GUI in the 2016.4 release of Vivado.
Prior to 2016.4 you'll have to use a non-OOC flow to modify the mig_7series_0_mig.v file in order for the changes to propagate through the rest of the design.
The best way to determine how many commands can be stored is to simulate the workload in question and observe the interface behavior.For information on the Reordering Logic, see (Xilinx Answer 34942).