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AR# 35422

Virtex-6 FPGA Integrated Block Wrapper for PCI Express - v1.3 Rev 1 Patch for ISE Design Suite 12.1

Description


There is now a v1.3 rev 2 patch available. Please use v1.3 rev 2 for all ES silicon applications; see (Xilinx Answer 36552).

The information about the v1.3 rev 1 patch is preserved here for version control purposes, but users need to update to v1.3 rev 2.

This is a patch for theVirtex-6 FPGA Integrated Block Wrapper v1.3 for PCI Express. This is the v1.3 rev 1 patch and is to be installed on ISE Design Suite 12.1. This patch resolves the following three issues:

CR 543565: MMCM VCO changed from 500 MHz to 1000 MHz.
The MMCM VC0 setting has been changed from 500 MHz to 1000 MHz due to new MMCM requirements

CR 551390: Fix for HDL compiler warnings.
Issue resolved where HDL compiler warnings were issued during Core Generation

CR 558536: Disable Lane Reversal Setting for Endpoint Configuration.
Disable Lane Reversal Attribute setting on the Integrated Block has been set to FALSE for Endpoint Configurations, per CES Errata.

For other v1.3 known issues, see (Xilinx Answer 33276).

Solution

To download this patch, see (Xilinx Answer 34279). This Answer Record includes a list of all updates for the Virtex-6 FPGAIntegrated Block Wrapper.

Revision History
09/15/2010 - Corrected link to Answer Record 36552
07/01/2010 - Updated information regarding v1.3 rev 2 availability
05/03/2010 - Initial Release

Linked Answer Records

Master Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
36552 Virtex-6 FPGA Integrated Block Wrapper v1.3 for PCI Express - v1.3 Rev 2 Patch for ISE Design Suite 12.1 N/A N/A
AR# 35422
Date Created 05/04/2010
Last Updated 05/20/2012
Status Active
Type Known Issues
Devices
  • Virtex-6 LXT
Tools
  • ISE Design Suite - 12.1
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )