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AR# 35425

Virtex-6 GTX - max data rate and max USRCLK2 frequency

Description

Can I use a 16 bits wide internal bus when serial data rate is set to 6.6 Gbps?

Solution

Recently, the Virtex-6 FPGA serial interface data rate has been improved from 6.5 Gbps to 6.6 Gbps.
The USRCLK max frequency has not been modified.
In order to sustain the improved throughput only the 20-bit data width and not the 16-bit data width is allowed.
In particular for USRCLK, the following frequency limits are still valid:

Speed grade

-3

-2

-1

RXUSRCLK/RXUSRCLK2 maximum frequency[MHz]

406.25

406.25

312.5

TXUSRCLK/TXUSRCLK2 maximum frequency[MHz]

406.25

406.25

312.5

Example:
6.6 Gbps serial data rate wants a internal speed of 330 MHz if the bus is 20 bits wide. This is supported in -2 and -3 speed grade silicon.
6.6 Gbps serial data rate and 16 bits internal fabric interface would need USRCLK2 frequency of 412.5 MHz; this is NOT supported.

AR# 35425
Date Created 04/28/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 LXT
  • Virtex-6 SXT