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AR# 35436

LogiCORE IP Video Timing Controller v2.0 - Why am I having problems reading the Interrupt Status Registers?

Description

Why am I having problems reading the Interrupt Status Registers?

Solution

This is a known problem that is addressed in the Video Timing Controller v2.1.

The problem is that the Timing Controller documentation and xtimebase_hw.h are pointing to the wrong offset.

In the Timing Controller documentation for Table 13 the ISR should be 0x120 and 0x128.

  Table 20 on page 19 should refer to address 0x120
  Table 21 on page 20 should refer to address 0x128

Users will also need to modify the xtimebase_hw.h on lines 105-107.

  Address 0x220 should be changed to 0x120
  Address 0x228 should be changed to 0x128

Users will also need to manage the interrupt-related registers from 0x100 to 0x11c.

You can find more information in the Interrupt Controller docs.

http://www.xilinx.com/support/documentation/ip_documentation/xps_intc.pdf


Please see (Xilinx Answer 32754) for a detailed list of LogiCORE Video Timing Controller Release Notes and Known Issues.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
32754 LogiCORE IP Video Timing Controller - Release Notes and Known Issues N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
32754 LogiCORE IP Video Timing Controller - Release Notes and Known Issues N/A N/A
AR# 35436
Date Created 04/28/2010
Last Updated 05/26/2014
Status Archive
Type General Article
IP
  • Video Timing Controller