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AR# 35441

Xilinx ISE Implementation Tool Solution Center - Route Section of Design Assistant

Description





Please refer to the following  to learn more about the ROUTE section of the Xilinx ISE Implementation Tools or to find help on debugging an issue you are currently encountering.  

Note: This Answer Record is a part of the Design Assistant section (Xilinx Answer 34756) of the Xilinx ISE Implementation Tool Solution Center (Xilinx Answer 34752) The Xilinx ISE Implementation Tool Solution Center is available to address questions related to Xilinx ISE Implementation Tools. 

Solution

Explanation of ROUTE tool functions:

See (Xilinx Answer 35540) for explanation of the "intermediate status" message.
See (Xilinx Answer 35556) for information about controlling routing for critical paths with Directed Routing constraints.

Debugging Tips for Route Issues:

See (Xilinx Answer 21723) for information on debugging Route:455 warnings about skew.

High Frequency Route Issues:

See (Xilinx Answer 33153) for help with the ParHelpers:79 warning message.
See (Xilinx Answer 29415) for information on hold time routing.

Latest Route Issues:

See (Xilinx Answer 33153) for help with the ParHelpers:79 warning message.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34752 Xilinx ISE Implementation Tools Solution Center N/A N/A
34756 Xilinx ISE Implementation Tools Solution Center - Design Assistant N/A N/A
AR# 35441
Date 04/04/2017
Status Active
Type General Article
Devices
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Spartan-3
  • Spartan-3 XA
  • Spartan-3A
  • Spartan-3A DSP
  • Spartan-3AN
  • Spartan-3E
  • Spartan-6 LX
  • Spartan-6 LXT
  • Less
Tools
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • Less