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AR# 35453

12.1 SP601 - NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin" CLOCK_DEDICATED_ROUTE = FALSE;


The following error is seen while implementing the BIST design in EDK 12.1

There is only a select set of IOBs that can use the fast path to the Clocker buffer, and they are not being used. You may want to analyze why this problem exists and correct it. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule. NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin" CLOCK_DEDICATED_ROUTE = FALSE;


Instead of using the suggestion generated by the tool, it is recommended that the following constraints be added to the UCF to achieve optimum timing.

NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin" CLOCK_DEDICATED_ROUTE = FALSE;

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33225 Spartan-6 FPGA SP601 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 35453
Date 05/20/2012
Status Active
Type Known Issues
  • Spartan-6 LX
  • ISE Design Suite - 12.1
  • XPS Ethernet Lite
Boards & Kits
  • Spartan-6 FPGA SP601 Evaluation Kit