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AR# 35461

11.5 Project Navigator - Regenerating Clocking Wizard core in wave_gen ISE Example fails

Description

I have opened one of the wave_gen_* ISE Example designs.

When I attempt to regenerate the clk_core IP core or try to run "Regenerate All Cores", numerous errors are generated due to read-only files in the project directory structure:

Preparing output directory...

ERROR:sim:452 - Found read only output file './clk_core\clk_core.ucf'. Please modify this file's permissions to allow write access.

ERROR:sim:452 - Found read only output file './clk_core\clk_wiz_readme.txt'.

Please modify this file's permissions to allow write access.

ERROR:sim:452 - Found read only output file

'./clk_core\example_design\clk_core_exdes.v'. Please modify this file's permissions to allow write access.

'./clk_core\example_design\clk_core_exdes.vhd'. Please modify this file's permissions to allow write access.

ERROR:sim:452 - Found read only output fileERROR:sim:452 - Found read only output file

'./clk_core\implement\implement.bat'. Please modify this file's permissions to allow write access.

ERROR:sim:452 - Found read only output file './clk_core\implement\implement.sh'.

Please modify this file's permissions to allow write access.

ERROR:sim:452 - Found read only output file './clk_core\implement\xst.prj'.

Please modify this file's permissions to allow write access.

ERROR:sim:452 - Found read only output file './clk_core\implement\xst.scr'.

Please modify this file's permissions to allow write access.

ERROR:sim:452 - Found read only output file

'./clk_core\simulation\clk_core_tb.v'. Please modify this file's permissions to allow write access.

ERROR:sim:452 - Found read only output file

'./clk_core\simulation\clk_core_tb.vhd'. Please modify this file's permissions to allow write access.

ERROR:sim:452 - Found read only output file

'./clk_core\simulation\functional\simcmds.tcl'. Please modify this file's permissions to allow write access.

ERROR:sim:452 - Found read only output file

'./clk_core\simulation\functional\simulate_isim.sh'. Please modify this

file's permissions to allow write access.

ERROR:sim:452 - Found read only output file

'./clk_core\simulation\functional\simulate_mti.do'. Please modify this file's permissions to allow write access.

ERROR:sim:452 - Found read only output file

'./clk_core\simulation\functional\simulate_ncsim.sh'. Please modify this

file's permissions to allow write access.

ERROR:sim:452 - Found read only output file

'./clk_core\simulation\functional\simulate_vcs.sh'. Please modify this file's permissions to allow write access.

ERROR:sim:452 - Found read only output file

'./clk_core\simulation\functional\ucli_commands.key'. Please modify this

file's permissions to allow write access.

ERROR:sim:452 - Found read only output file

'./clk_core\simulation\functional\vcs_session.tcl'. Please modify this file's permissions to allow write access.

ERROR:sim:452 - Found read only output file

'./clk_core\simulation\functional\wave.do'. Please modify this file's permissions to allow write access.

ERROR:sim:452 - Found read only output file

'./clk_core\simulation\functional\wave.sv'. Please modify this file's permissions to allow write access.

ERROR:sim - output directory contains read only content.

ERROR:sim - Failed to generate 'clk_core'.

ERROR:sim:549 - Error found during execution of IP clk_core (Clocking Wizard version 1.5)

Solution

Many of the files under the wave_gen_*/ipcores_dir/clk_core directory were incorrectly delivered with READ Only permissions.

The design will synthesize and implement correctly. However, if a user attempts to overwrite the clk_core files by regenerating the core, the file permission errors are issued.


To fix the problem, run chmod recursively on the clk_core directory or use the Windows properties option to give READ/WRITE permissions to all file under the ipcores_dir/clk_core directory.

AR# 35461
Date Created 04/28/2010
Last Updated 09/24/2015
Status Active
Type General Article
Tools
  • ISE Design Suite - 11.5