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AR# 35480

Spartan-6 PLL - Timing Analyzed Incorrectly When Using CLKOUT0 as Feedback

Description

The ISE 12.1 and earlier software tools incorrectly analyze the timing of the PLL VCO when CLKOUT0 feedback is used.

Solution

The default and most commonly used feedback path for the PLL is the CLKFBOUT output. The design tools properly calculate all timing when CLKFBOUT is used as feedback. However, in the case where CLKOUT0 is used for feedback, the calculation of the VCO value is done incorrectly in the ISE 12.1 and earlier software.

The Spartan-6 FPGA Clocking Resources User Guide (UG382 v1.3.1) describes the correct equations.

When CLK_FEEDBACK = CLKFBOUT, use Equation 3-7 from UG382:

FVCO = FCLKIN x M/D

When CLK_FEEDBACK = CLKOUT0, use Equation 3-8 from UG382:

FVCO = FCLKIN x (MxO)/D

Given:

O = the output divide value of CLOUT0
M = CLKFBOUT_MULT value
FVCO = the frequency of the PLL voltage controlled oscillator
FCLKIN = input clock to the PLL
D = divide value

The software tools omit the "M" value from equation 3-8 when CLKOUT0 is used. If M is set to "1" (default) in the design, the calculations will be made correctly. If M is other than "1", the timing analysis in the software will be incorrect.

This issue will be fixed in the ISE 12.2 software tools.

AR# 35480
Date Created 04/29/2010
Last Updated 05/20/2010
Status Active
Type General Article
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
Tools
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • Less