AR# 35504: 11.5 MAP - What is the difference between the "S" (Save) and "KEEP" constraint?
11.5 MAP - What is the difference between the "S" (Save) and "KEEP" constraint?
I have some unused logic in a module in my design that is being trimmed. I would like to prevent the trimming for now until I get the module connected properly. I am confused about whether to use the "S" constraint or the "KEEP" constraint. Which of these constraints will affect trimming?
The "S" property is the correct property to use to block logic trimming. The functionality of the "S" property was expanded in ISE 10.1 software so that it will also block constant optimization from propagating through the net and logic connected to a net with an "S" property will not be removed. Also, "S" properties can be applied directly to logical instances to prevent their removal.
The "KEEP" net property has a different purpose and can be thought of as a packing constraint. It is used to keep a signal from being entirely merged into a component so that the signal would not exist in the physical design. It has no effect on the trimming of unused logic or on constant optimization. It can be used to control packing behavior, but only to the extent that it blocks packs that would otherwise cause the signal to disappear.
See (Xilinx Answer 30112) for an explanation of the new "S" property behavior introduced in ISE 10.1 software and some of the problems that can result from their use.