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AR# 35506

ISE MAP - How do I debug a DRC error?

Description

My design is getting a DRC error that halts the MAP process.

I do not entirely understand the error message and since MAP failed there is no NCD file to examine for debug purposes.

Is there a way to bypass the error so that I can examine the physical design in FPGA Editor?

Solution


It is possible to bypass DRC errors for debug purposes.

Both the logical and physical DRC checks can be disabled with environment variables.

Logical DRC errors contain the string "LIT", whereas Physical DRC errors contain the string "PhysDesignRules".
 

To disable Logical DRC checks:
 
Windows

SET XIL_MAP_SKIP_LOGICAL_DRC=1


Linux

setenv XIL_MAP_SKIP_LOGICAL_DRC 1


To disable Physical DRC checks:
 
Windows

SET XIL_MAP_NODRC=1

Linux

setenv XIL_MAP_NODRC 1


For more information on DRC checks, see (Xilinx Answer 35505).
 
For general information about setting ISE environment variables, see (Xilinx Answer 11630).
AR# 35506
Date Created 05/06/2010
Last Updated 02/19/2015
Status Active
Type General Article
Devices
  • FPGA Device Families
Tools
  • ISE