My design fails during placement with a "Place:543" error. The message is quite verbose and I am unable to understand it.
How can I make use of the information in this message to solve my problem?
"ERROR:Place:543 - This design does not fit into the number of slices available in this device due to the complexity of the design and/or constraints.
Unplaced instances by type: FF 100 (2.0%)
Please evaluate the following:
- If there are user-defined constraints or area groups:
Please look at the "User-defined constraints" section below to determine what constraints might be impacting the fitting of this design.
Evaluate if they can be moved, removed or resized to allow for fitting.
Verify that they do not overlap or conflict with clock region restrictions.
See the clock region reports in the MAP log file (*map) for more details on clock region usage.
- If there is difficulty in placing LUTs:
Try using the MAP LUT Combining Option (map lc area|auto|off).
- If there is difficulty in placing FFs:
Evaluate the number and configuration of the control sets in your design.
The following instances are the last set of instances that failed to place:
0. FF ImplementSampler.i_Sampler/i_input_mux/i_FB_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/count_d3<8>
1. FF ImplementSampler.i_Sampler/i_DDR2_top/U_0/u_mem_if_top/u_phy_top/phy_init_ras_n
2. FF ImplementSampler.i_Sampler/i_DDR2_top/U_0/u_mem_if_top/u_phy_top/u_phy_init/phy_init_done_r
3. FF i_EthernetInterface/i_eth_cosim_core/v5_emac_ll/client_side_FIFO_emac1/tx_fifo_i/wr_eof_pipe(1)
... (100 instances listed)
These instances could be impacted by the following constraints (the line IDs below correspond with the instances above):
31. < COMPGRP "CLKAG_ImplementCPRI.cpri_top_i/tx_clk_int.SLICE" LOC = SLICE_X0Y0:SLICE_X47Y19,SLICE_X48Y0:SLICE_X91Y19, SLICE_X0Y20:SLICE_X47Y39,SLICE_X48Y20:SLICE_X91Y39,SLICE_X0Y40:SLICE_X47Y59,SLICE_X4... >
32. < COMPGRP "CLKAG_ImplementCPRI.cpri_top_i/tx_clk_int.SLICE" LOC = SLICE_X0Y0:SLICE_X47Y19,SLICE_X48Y0:SLICE_X91Y19, SLICE_X0Y20:SLICE_X47Y39,SLICE_X48Y20:SLICE_X91Y39,SLICE_X0Y40:SLICE_X47Y59,SLICE_X4... >
... (more constraints listed)"
This message is printed when a design fails to fit, meaning that for some number of components no legal site placement was found. To understand the root cause of the failure, it is necessary to understand what components are failing to fit and then what pack/place restrictions apply to those components that make their fitting difficult. Once the restrictions are understood it is possible to look for ways of relieving restrictions.
Identifying the Logic Involved
The components listed in the Place:543 message are physical components whose name is usually not the same as the name of the instance in the logical netlist. Instead, the name is derived from an output net name. So, when trying to correlate a FF component back to the logical design, find the net with the same name in the logical design and then examine the FF driving it.
Identifying the Pack/Place restrictions on the Component
There are a number of restrictions that can apply to a FF component for example:
Look for Commonality Between the Components that Failed to Fit and Try to Relax the Placement Restrictions.