My design fails in MAP with the following Place errors:
ERROR:Place:740 - Clock Placer failed to ensure a clocking rule was followed
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
What do these messages mean and what can I do to resolve the issue?
The error message indicates that the clock placer failed to find a good placement for the clock components, but the messaging is poor in that it does not report the specific issue.
All cases seen with this error have involved DCM/PLL circuits. The most recent case was an infeasible circuit because there were 3 DCMs trying to connect to one PLL. The DCMs and PLL need to be on the same half of the device, but there are only two PLLs per side in the device (involved V5LX30).
Since there are 3 DCM's, the solution is to instantiate another PLL so that one of DCMs can be paired with the 2nd PLL on the other half of the device.
A CR is currently under investigation for the messaging issue.