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AR# 35566

MIG Virtex-6-DDR3 - simulation does not support Burst Length OTF (on the fly)


MIG simulation does not support Burst Length OTF (on the fly) for both VHDL and Verilog. 


This is only an issue with the MIG generated traffic generator available in the example design as the user design works with Burst Length OTF.

If simulations are run with Burst Length OTF the following failure behavior will occur:

  1. For VHDL simulation, Burst Length 8 will be used by default and no errors will occur.
  2. For Verilog simulation, simulations will stop with a message that the current traffic generator does not support OTF Burst Mode.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
39128 MIG Virtex-6 and Spartan-6 v3.7 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A
AR# 35566
Date 09/03/2014
Status Active
Type Known Issues
  • Virtex-6 LXT
  • Virtex-6 CXT
  • Virtex-6 HXT
  • More
  • Virtex-6 LX
  • Virtex-6 SXT
  • Less
  • ISE Design Suite - 12.1
  • ISE Design Suite - 11.5
  • MIG
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