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AR# 35570

Serial RapidIO v5.5 - Port_initialized fails to assert in Virtex-6 FPGA Core

Description

An issue has been seen in Virtex-6 FPGAthat causes the port_initialized signal to fail to go High in designs using 1.25G and 2.5G line rates.

Solution

The problem is that the TXRESETDONE signal from the GTs fails to assert. This is due to the issue described in (Xilinx Answer 35681). The work-around required for the Xilinx Serial RapidIO solution is different depending on the line rate being used.

For 2.5G:

Modify the GT settings so that a lower VCO rate is used. Specifically, the settings should be changed back to the values that were used and tested in v5.4 and earlier of the Core:

Correct Settings (v5.4) Failing Settings (v5.5)
TXPLL_CP_CFG 39 0D
TXPLL_DIVSEL_OUT 1 2
TXPLL_DIVSEL_FB 2 4
RXPLL_DIVSEL_REF 1 1
RXPLL_DIVSEL45_FB 5 5
RXPLL_DIVSEL_FB 2 4
RXPLL_DIVSEL_OUT 1 2
VCO (GHz) 1.25 2.5
RXPLL_CP_CFG 39 0D

For 1.25G:

The VCO cannot be lowered at 1.25G and the user must implement the double GTXTEST pulse as described in (Xilinx Answer 35681).

This issue is to be fixed in the next release of the Core (v5.6) which is currently scheduled for the ISE 13.1 software release.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
40519 Serial RapidIO v5.6 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A

Associated Answer Records

AR# 35570
Date Created 05/19/2010
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • Serial RapidIO