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AR# 35571

12.1 ISE Simulator (ISim) - ERROR: Can not find hierarchical name STARTUP_V6_PWRUP_GTXE1_ML_INSERTED in the current scope.

Description

I have followed the directions shown in Xilinx Answer 35514 to remove all the auto-inserted primitives from the simulation netlist. However, when I launch a Post-Route (Timing) simulation in ISim, I encounter the following error:

ERROR: Can not find hierarchical name STARTUP_V6_PWRUP_GTXE1_ML_INSERTED in the current scope.
ERROR: (SdfError)While back annotating file "netgen/par/wave_gen_timesim.sdf", cell instance STARTUP_V6_PWRUP_GTXE1_ML_INSERTED not found in design.

Back-annotation is then unsuccessful and cannot properly perform a timing simulation of the design.

How can I resolve this issue?

Solution

This error can occur if theXIL_NETGEN_REMOVE_GTXE1 environment variable is set but the required patch (Step 2 in Xilinx Answer 35514) has not been properly installed. Please make sure you follow the patch installation instructions (readme.txt) properly.

For further assistance with this issue, please contact Xilinx Technical Support using the contact methods in the Support page.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
35514 12.1 - Timing simulation issue when targeting Virtex-6 devices N/A N/A
AR# 35571
Date Created 05/06/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
Tools
  • ISE Design Suite - 12.1