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AR# 35685

MIG Spartan-6 MCB DDR2/DDR3 - Is there any requirement for the MCB sys_rst signal?


Within the Spartan-6 FPGA Memory Controller User Guide and  Spartan-6 FPGA Memory Interface Solutions User Guide, there are no requirements regarding sys_rst.

Is there any requirement for this reset?


Sys_rst is the reset signal used within the MIG IP to re-initialize the IP.

The reset signal is used by the MIG PLL input, so it is same as the PLL reset input requirement.

It is an async signal and there is no clock cycle requirement.

However, there is a minimum reset pulse width requirement for PLL.

You will need to ensure that this requirement is met.


AR# 35685
Date 09/10/2014
Status Active
Type General Article
  • Spartan-6 LXT
  • ISE Design Suite - 12.1
  • MIG
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