AR# 35741

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12.1 EDK - ERROR:EDK - xget_handle parent : A NULL handle was provided

Description

When running Generate Libraries and BSP, I receive the following error:

lwIP can be used with the following EMAC peripherals found in your system:
xps_ll_temac_0
ERROR:EDK - xget_handle parent : A NULL handle was provided
ERROR:EDK - lwip130 () - expected integer but got ""
ERROR:EDK:1191 - Error(s) while running DRCs for processor microblaze_0.
make: *** [microblaze_0/lib/libxil.a] Error 2
Done!

Why am I receiving the errors and how can they be resolved?

Solution

The error messages shown above are due to the LwIP Tcl file expecting a set of parameters that do not exist (they return 'NULL). One known reason for the error messages is due to a missing Local Link Bus connection on the xps_ll_temac.

For example, the following .MHS snippet demonstrates a xps_ll_temac instance that will cause the errors:

BEGIN xps_ll_temac
PARAMETER INSTANCE = Hard_Ethernet_MAC
PARAMETER C_NUM_IDELAYCTRL = 2
PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y3-IDELAYCTRL_X1Y4
PARAMETER C_PHY_TYPE = 1
PARAMETER C_TEMAC1_ENABLED = 0
PARAMETER C_BUS2CORE_CLK_RATIO = 1
PARAMETER C_TEMAC_TYPE = 0
PARAMETER C_TEMAC0_PHYADDR = 0b00001
PARAMETER HW_VER = 2.03.a
PARAMETER C_BASEADDR = 0x90600000
PARAMETER C_HIGHADDR = 0x9067ffff
BUS_INTERFACE SPLB = mb_plb
PORT TemacIntc0_Irpt = Hard_Ethernet_MAC_TemacIntc0_Irpt
PORT TemacPhy_RST_n = fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin
PORT GTX_CLK_0 = clk_125_0000MHzPLL0
PORT REFCLK = clk_200_0000MHz
PORT MII_TX_CLK_0 = fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin
PORT GMII_TXD_0 = fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin
PORT GMII_TX_EN_0 = fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin
PORT GMII_TX_ER_0 = fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin
PORT GMII_TX_CLK_0 = fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin
PORT GMII_RXD_0 = fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin
PORT GMII_RX_DV_0 = fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin
PORT GMII_RX_ER_0 = fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin
PORT GMII_RX_CLK_0 = fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin
PORT MDC_0 = fpga_0_Hard_Ethernet_MAC_MDC_0_pin
PORT MDIO_0 = fpga_0_Hard_Ethernet_MAC_MDIO_0_pin
END

This can be fixed by adding a Local Link Interface connection and a Local Link clock. The other end of the Local Link will also need to be connected to a Local Link FIFO, MPMC, or some other pcore that includes a Local Link interface. Below is an updated example that should no longer produce the error messages:

BEGIN xps_ll_temac
PARAMETER INSTANCE = Hard_Ethernet_MAC
PARAMETER C_NUM_IDELAYCTRL = 2
PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y3-IDELAYCTRL_X1Y4
PARAMETER C_PHY_TYPE = 1
PARAMETER C_TEMAC1_ENABLED = 0
PARAMETER C_BUS2CORE_CLK_RATIO = 1
PARAMETER C_TEMAC_TYPE = 0
PARAMETER C_TEMAC0_PHYADDR = 0b00001
PARAMETER HW_VER = 2.03.a
PARAMETER C_BASEADDR = 0x90600000
PARAMETER C_HIGHADDR = 0x9067ffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE LLINK0 = Hard_Ethernet_MAC_llink0 #ADD LOCAL LINK BUS INTERFACE
PORT TemacIntc0_Irpt = Hard_Ethernet_MAC_TemacIntc0_Irpt
PORT TemacPhy_RST_n = fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin
PORT GTX_CLK_0 = clk_125_0000MHzPLL0
PORT REFCLK = clk_200_0000MHz
PORT LlinkTemac0_CLK = clk_125_0000MHzPLL0 #ADD LOCAL LINK CLOCK
PORT MII_TX_CLK_0 = fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin
PORT GMII_TXD_0 = fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin
PORT GMII_TX_EN_0 = fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin
PORT GMII_TX_ER_0 = fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin
PORT GMII_TX_CLK_0 = fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin
PORT GMII_RXD_0 = fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin
PORT GMII_RX_DV_0 = fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin
PORT GMII_RX_ER_0 = fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin
PORT GMII_RX_CLK_0 = fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin
PORT MDC_0 = fpga_0_Hard_Ethernet_MAC_MDC_0_pin
PORT MDIO_0 = fpga_0_Hard_Ethernet_MAC_MDIO_0_pin
END

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34609 12.x EDK - Master Answer Record List N/A N/A
AR# 35741
Date 12/15/2012
Status Active
Type General Article
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