We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 35781

How to do simulation on DCM/PLL/MMCM with external feedback?


If the DCM/PLL/MMCM is configured as external feedback, how do you simulate it?


To simulate external feedback you can add the external board delay in the testbench.

For VHDL: the keyword "transport" should be used in testbench. FBIN <= transport FBOUT after 1ns;

For Verilog: assign FBIN = #1ns FBOUT;

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
46790 Spartan-6 FPGA Design Assistant - Troubleshooting Common Clocking Problems N/A N/A
AR# 35781
Date 03/07/2013
Status Active
Type General Article
  • Spartan-3
  • Spartan-3E
  • Spartan-3A
  • More
  • Spartan-6 LX
  • Spartan-6 LXT
  • Virtex-4 LX
  • Virtex-4 FX
  • Virtex-4 QPro/R
  • Virtex-4 SX
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Spartan-3A DSP
  • Spartan-3AN
  • Less
  • Digital Clock Manager (DCM) Module
  • PLL Module
Page Bookmarked