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AR# 35793

MIG Virtex-6 DDR2/DDR3 - Read Latency

Description

This section of the MIG Design Assistant focuses on Read Latency of the Virtex-6 DDR3/DDR2 designs. See below to find information related to your specific question.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

Read latency is measured from the point where the read command is accepted by the User Interface (or native interface) and when the Read data is received. Below are several parameters that can vary the Read Latency:

The number of commands already in the pipeline before the read command is issued

Whether an ACTIVATE command needs to be issued to open the new bank/row

Whether a PRECHARGE command needs to be issued to close a previously opened Bank

Specific timing parameters for the memory, such as TRAS and TRCD in conjunction with the bus clock frequency

Commands can be interrupted, and banks/rows can forcibly be closed when the periodic AUTO REFRESH command is issued

CAS latency

For specific values in clock cycles and a further description of Read Latency for Virtex-6 DDR3/DDR2 designs, please refer to the "Virtex-6 FPGA Memory Interface Solutions" User Guide UG406, section "Read Latency:

http://www.xilinx.com/support/documentation/ip_documentation/ug406.pdf

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34282 MIG Design Assistant - Virtex-6 Core Functionality N/A N/A
34393 MIG Virtex-6 DDR2/DDR3 - Performance N/A N/A
AR# 35793
Date Created 05/25/2010
Last Updated 01/28/2013
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG