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AR# 35855

Virtex6 IODELAY- How much jitter will be introduced into IODELAY dataout?

Description

How much jitter will be introduced into IODELAY dataout?

Solution

It depends on the signal pattern and HIGH_PERFORMANCE mode setting.
For clock pattern, the jitter on IODELAY is zero regardless the HIGH_PERFORMANCE mode setting.
For random data pattern (PRBS23), the jitter on IODLEAY is +/- 5ps per tap if the HIGH_PERFORMANCE mode is set to HIGH and is +/- 9ps per tap if the HIGH_PERFORMANCE mode is set to FALSE.
AR# 35855
Date Created 05/24/2010
Last Updated 05/28/2010
Status Active
Type General Article
Devices
  • Spartan-6 LX
  • Spartan-6 LXT