Description

When Iruntiming nalysis on my Spartan-6 FPGA design,the Distributed LUT RAM (DRAM) elements and BlockRam (RAMB) are not constrained under the PERIOD/FROM:TO constraints, but under the unconstrained path section of the Timing Report.

This issue is fixed in ISE Design Suite12.3 and later.

Solution

This is a known issue in ISE Design Suite 12.1. The DRAM/RAMB elements are not included in the correct TimeGroups (TNM/TNM_NET), which causes the timing constraints (PERIOD/FROM:TO) to be analyzed incorrectly. Some of the primitives were fixed in ISE 12.2 software.

There are two optional work-arounds:

• Manually constrain the path to the DRAMs using FROM-TO or MAXDELAY constraints.
• Usea TPSYNC constraint to group the DRAMs (as opposed to a TNM constraint).

For example:
INST "instance_name" TPSYNC = "Group";

This can be used within a FROM_TO constraint.

This issue is fixed in ISE Design Suite12.3.

To determine if this issue affects your design, please review the MAP report and the Timing Report.

The following primitives were missing in 12.2, but fixed in 12.3:

+RAM16X1D
+RAM16X1D_1
+RAM32X1D
+RAM32X1D_1
+RAM64X1D
+RAM64X1D_1
+RAM128X1D
+RAM64X1Q

The following primitives were missing in 12.1, but fixed in 12.2:

+RAM16X1S
+ RAM32X1S
+ RAM32M
+ RAM64M
+ RAMB16_S1_S1
+ RAMB16_S4_S4
+ RAMB16_S9_S9
+ RAMB16_S18
+ RAMB16_S18_S18

Linked Answer Records

Master Answer Records

Associated Answer Records